Summary
A ferroelectric field-effect transistor (FeFET) is an ordinary transistor with a ferroelectric layer inserted into the gate stack. Applying a gate voltage above the coercive field flips the layer’s remanent polarisation, and that polarisation screens or reinforces the channel charge, shifting the device threshold voltage. The stored bit is read by sensing whether the transistor conducts at a given gate bias, so the read is non-destructive and does not disturb the state. Because the storage element is inside the gate rather than a separate capacitor or resistor, a cell can in principle be a single transistor, which is the density argument. The technology became interesting again when ferroelectricity was found in doped hafnium oxide, which unlike legacy PZT is compatible with CMOS and back-end-of-line processing and scales below 10 nm.
Two application vectors dominate the literature. The first is embedded non-volatile memory to replace embedded flash, which stops scaling around 28/22 nm for cost rather than physics reasons, plus dense BEOL RAM: an IGZO FeFET NOR bitcell has been projected down to roughly 0.016 um2, equivalent to a 10-transistor SRAM area at 7 nm ground rules, with sub-5 ns random access. The second is compute-in-memory, where FeFET appears repeatedly as one device option alongside ReRAM, PCM, MRAM and SRAM in heterogeneous processing-in-memory accelerators.
A separate research line uses the FeFET geometry as a measurement tool rather than a memory: sliding ferroelectricity in CVD-grown 3R-stacked WSe2 bilayers probed through a graphene ferroelectric-FET, where graphene senses polarisation-induced charge modulation and the study focuses on how structural disorder and multi-domain kinetics degrade switching. That is a different materials family from hafnia and should not be read as evidence about product-grade FeFET.
Evidence base
Open questions
Assessment drafted 2026-08-31 from up to 11 KB sources using the technology-scorecard framework; scores are a draft read pending review.