In-memory computing performs arithmetic inside the memory array itself, using the physics of resistive, ferroelectric, magnetic or photonic memory cells to do matrix-vector multiplication where the data already sits, and it is now producing fabricated chips in narrow edge roles while its large datacentre efficiency claims remain simulation-bound.
Summary
The consequence is that IMC is currently strongest where the workload is small, fixed, tolerant of noise and starved of power: an implanted 32-channel brain-machine interface SoC in 65 nm CMOS uses an IMC spike detector and runs at 3.53 uW per channel with 0.034 mm2 per channel. The large claims, LLM inference acceleration and Monte Carlo tree search at tens of milliwatts, sit at the architecture-simulation level with fabricated device parameters as inputs.
Evidence base
- 2026-07-28: An RRAM-based multi-primitive IMC design runs 9x9 Go Monte Carlo tree search at about 60 mW at 22 nm with fabricated array parameters, reported at 96x CPU and 65x-2,059x H100 energy efficiency, and reaches a Go rating within sample-size uncertainty of open-source engines.
- 2026-06-02: A fabricated 32-channel event-based implant SoC in 65 nm CMOS with an IMC spike detector consumes 3.53 uW per channel, gives up to 26x frontend data compression and achieves about 0.62 decoding R2 in 0.034 mm2 per channel.
- 2026-06-03: Ferroelectric HfO2/ZrO2 layers integrated in the CMOS back end achieve 1 ns multi-level writes below 5 V, endurance above 10^11 cycles and 10-year retention, but the memory window collapses above 1 MHz read frequency, requiring a new 20 ps non-destructive readout method.
- 2026-07-29: On a 65 nm single-poly floating-gate analog IMC array, circuit compensation plus batch-normalisation recalibration recovers baseline inference accuracy to within 2-4% sixty days after programming on VGG-10/CIFAR-10 and WideResNet-28-10/CIFAR-100.
- 2026-06-07: A fabricated 1x256-bit single-wavelength photonic SRAM array on a standard GlobalFoundries silicon photonics process sustains 1.5, 0.9 and 1.3 TOPS on three HPC kernels at an average 2.5 TOPS/W once external memory access and opto-electronic conversion overheads are modelled.
- 2026-06-05: A PIM co-design for graph-based approximate nearest neighbour search shrinks the PIM-resident index footprint by 14.5x, addressing a workload where CPU throughput is capped by main-memory bandwidth and GPUs lack the HBM capacity for billion-scale indexes.
Open questions
Assessment drafted 2026-08-31 from up to 18 KB sources using the technology-scorecard framework; scores are a draft read pending review.