Embedded non-volatile memory (eNVM) refers to NVM arrays integrated monolithically on the same die as logic, in contrast to stand-alone (discrete) memory chips. In a standard SoC the eNVM holds firmware, model weights, calibration constants, and secure boot keys. The dominant incumbent is embedded flash (eFlash), which uses floating-gate or charge-trap transistors; it does not scale cleanly below 28 nm because the tunnel oxide cannot be thinned without catastrophic leakage, and the high programming voltages it requires (12–18 V) are incompatible with advanced-node transistors.
The scaling wall is the core investment signal. As logic migrates to 22 nm and below — driven by edge-AI, automotive MCUs, and IoT — eFlash cannot follow, opening sockets for alternatives. The main contenders are: MRAM (high endurance, fast write, radiation-hard, scales to 22 nm BEOL), FeRAM / FeFET (ultralow write energy via spontaneous polarisation in HfO₂, CMOS-compatible BEOL), RRAM/ReRAM (resistive switching, high density, natural analog compute substrate), and PCM (high density, multibit per cell).
CMOS-compatibility and BEOL integration are the killer feature requirements: an eNVM that demands a separate mask or exotic front-end chemistry cannot be economically embedded. Ferroelectric HfO2 is significant here because HfO₂ is already a gate-dielectric material in sub-28 nm nodes — FeRAM and FeFET inherit that integration path at zero added process complexity.
Frontier
- Which NVM technology — MRAM, FeRAM/FeFET, or RRAM — takes embedded-flash’s socket below 22 nm, and which foundry qualification comes first (TSMC eMRAM, GF FeRAM, or a fabless IP licensor)?
- At what node does retention-endurance co-optimisation become a hard ceiling for FeFET in automotive-grade eNVM (AEC-Q100 Level 1 requires 10-year retention at 150 °C)?
- Can compute-in-memory (CIM) architectures move eNVM from a storage function to an active compute substrate, and does that create the same market as In-Memory Computing?