OSAT firms are the contract manufacturers that dice, package and test finished chips for others, and the AI-driven shift of packaging from a commodity step to a 2.5D/3D advanced-packaging market forecast at $80B by 2030 is the event that decides whether that tier gains or loses relevance.
Summary
OSAT stands for Outsourced Semiconductor Assembly and Test. It is a business model rather than a device technology. A foundry or an integrated device manufacturer produces and probes wafers; an OSAT then takes those wafers, dices them, attaches the die to substrates or interposers, forms the interconnect (wire bond, flip chip, fan-out redistribution layers, through-silicon vias, die stacking), encapsulates and finally tests the packaged units. Historically this was the low-margin end of the chain: labour and capital arbitrage on a step that added little differentiated value, which is exactly why it was outsourced.
What changes that is the shift of system-level performance from the transistor to the interconnect. Advanced packaging is measured as a distinct market growing at a 9.6% CAGR from 2024 to 2030 to reach $80B by 2030, with 2.5D/3D identified as the fastest-expanding platform and AI as the driver; quarterly revenue was $13B in Q2 2025 with 13% sequential growth projected for Q3 2025 ref. The packaging step is now capable of being the binding constraint on a product line rather than a cost line: SemiAnalysis models CXMT going from 1% of global HBM wafer supply in 2025 to 12% by 2028 and states that the bottleneck is no longer ambition or capital but HBM stacking yield.
The parameters that decide the OSAT tier specifically are not the growth of packaging but where in the flow the hard steps sit. Wire bond and flip chip are die-level operations that an OSAT owns. Hybrid bonding, wafer-to-wafer and die-to-wafer bonding, micro-transfer printing and monolithic BEOL integration are wafer-level processes that look and behave like front-end lithography and are being demonstrated inside CMOS foundries and pilot lines, for example a 200 mm CMOS pilot line using micro-transfer printing as a back-end post-processing step and foundry-compatible BEOL post-processing for photonic MEMS switches. Every step that migrates to wafer level migrates away from the OSAT floor.
One terminology warning, because it explains why the source base around this concept is thin. The semiconductor industry uses “back end” for assembly and test (the OSAT domain) and “back end of line” or BEOL for the metallisation layers built on top of transistors inside the wafer fab. Most of the tier-1 literature returned for this concept concerns BEOL integration of new materials (ferroelectrics, IGZO, VO2, lithium niobate, diamond heat spreaders) and says nothing about outsourced assembly. Those papers are relevant only indirectly, as evidence about where integration value is accumulating.
Evidence base
- Advanced packaging grew at a 9.6% CAGR from 2024 to 2030 towards $80B by 2030, with 2.5D/3D the fastest-expanding platform driven by AI; Q2 2025 revenue was $13B with 13% sequential growth projected for Q3 2025 ref.
- SemiAnalysis models CXMT rising from 1% of global HBM wafer supply in 2025 to 12% by 2028, and states the bottleneck is no longer capital but HBM stacking yield.
- AI back-end network switch spending is forecast to pass $20B by 2028 and $100B by 2030, 1.6 Tbps switches ship in volume in 2026, and the market is supply-constrained rather than demand-constrained; the systems layer is judged incumbent-owned ref.
- A 200 mm CMOS pilot line demonstrated micro-transfer printing of active components onto dual-layer SiN as a wafer-scale back-end post-processing step, published August 2026.
- A zero-change foundry-compatible silicon photonics MEMS switch with over 30 dB extinction ratio, under 1.5 dB insertion loss and about 20 nW static power was produced using BEOL post-processing, August 2026.
- Monolithic 3D BEOL cache expansion from 40MB upwards is being evaluated as a route to cut off-chip HBM traffic in LLM serving, a substitution path that moves bandwidth value from packaging to wafer processing.
- A July 2026 report names advanced packaging among the “More than Moore” domains where competitive positions are still forming, alongside gaps in European funding velocity and exits.
Open questions
- What share of the $80B-by-2030 advanced-packaging market is booked by outsourced assemblers versus foundries and IDMs, and is that share rising or falling through 2028?
- Do hybrid bonding and die-to-wafer bonding settle inside wafer fabs, or do OSATs qualify them at volume and on cost?
- Is HBM stacking yield solved in-house by memory makers, or does it create a durable outsourced high-value test and stacking business?
- Are OSAT gross margins actually expanding with the 2.5D/3D mix shift, or is the mix shift being absorbed as capex intensity with flat margins?
Assessment drafted 2026-08-31 from up to 18 KB sources using the technology-scorecard framework; scores are a draft read pending review.