Advanced packaging is the set of techniques for wiring multiple dice together inside one package (2.5D interposers, 3D stacks, flip-chip, co-packaged optics) instead of shrinking one big die, and it has become the main lever for scaling AI compute now that monolithic scaling has stalled.
Summary
Advanced packaging covers everything that happens between the finished silicon die and the socket: bonding several dice side by side on a passive silicon interposer (2.5D), stacking active dice directly on top of one another with through-silicon vias (3D), flip-chip attachment of high-speed electrical interfaces to a photonic or electronic die, and co-packaging optics with the compute. The purpose is to build systems larger than the reticle limit while keeping yield tolerable, because a system assembled from small known-good dice loses less silicon to defects than one enormous die. The sources describe this as the standard route to “complex heterogeneous systems beyond the limits of monolithic scaling”, and treat multi-chiplet GPUs and 2.5D FPGAs as existing device classes rather than proposals.
The physics that decides it is interconnect and heat. Crossing between dice costs more energy and latency than staying on one die, so inter-die connection density and latency constrain the architecture and force a bespoke routing design. In multi-chiplet GPUs, memory splits into local and remote HBM regions across the interposer, and remote traffic for a single matrix multiplication can vary by up to 58x depending on kernel and placement choices. Heat is the second constraint: a stack contains materials whose feature sizes span many orders of magnitude, and the back-end-of-line metallisation structures repeated billions of times across a stack are described as a near insurmountable hurdle for analysis at the speed a design flow needs. Power delivery follows: through-silicon via placement determines effective resistance and IR drop across a 3D stack.
The parameters that decide how far this goes are therefore not fabrication alone. They are: how small a chiplet can economically be, which today is bounded near 100 mm2 by the area overhead of electrostatic discharge protection and inter-chiplet signalling circuitry; how much interconnect bandwidth per unit footprint the package substrate can carry while still dissipating heat; whether design tools can predict thermal, power and routing behaviour early enough to be useful; and whether software can be made to respect the resulting non-uniform memory system.
A distinct branch is packaging as an enabler for non-silicon dice: a flip-chip platform delivering 13 high-speed and 32 low-speed signals to a thin-film lithium niobate photonic chip with bandwidth to 50 GHz, and architectures that assume co-packaged optics as a given.
Evidence base
Open questions
- Can the ESD and inter-chiplet signalling simplifications proposed in survive real reliability qualification, and does chiplet area genuinely fall below 100 mm2 as a result?
- What is the thermal ceiling on 3D logic-on-logic stacks once the multiscale effects described in are accounted for, as opposed to bulk-property estimates?
- Does the cross-chiplet side-channel leakage demonstrated in force shielding, isolation or certification requirements on multi-vendor chiplet marketplaces, and at what area and cost penalty?
- Do simulated interconnect gains such as the 2.5x bandwidth and fourfold thermal improvement of the spoof-plasmonic structure survive fabrication at package scale?
Assessment drafted 2026-08-31 from up to 18 KB sources using the technology-scorecard framework; scores are a draft read pending review.