CoWoS is TSMC’s silicon-interposer packaging platform that bolts logic dies and HBM stacks into a single module, and through 2026 it is the physical chokepoint metering how many AI accelerators the world can build ref.
Summary
Modern AI accelerators are not single chips. A GPU or custom ASIC die is placed alongside several stacks of high-bandwidth memory on a silicon interposer, a passive slab of silicon carrying thousands of very fine wires, which is then mounted on an organic substrate. CoWoS is TSMC’s version of that assembly step. HBM itself is defined around it: stacked DRAM on through-silicon vias over a base die, co-packaged on a silicon interposer, with bus widths of 1,024 bits for HBM3E rising to 2,048 bits for HBM4. Without an interposer of this class there is no way to land that many parallel connections between logic and memory at acceptable energy per bit.
The technology is not experimental. It is high-volume manufacturing, and the interesting parameters are industrial rather than physical: how many interposer-equivalent units per month exist, who holds the allocation, and what the lead time is. On the supplied evidence, capacity is fully booked through 2026, lead times run 50 to 104 weeks, and Nvidia alone booked roughly 55% of 2026 output ref. Analysts consistently argue the gating constraint on HBM-based systems is the packaging, not the memory die, and Yole names TSMC CoWoS capacity as the leading bottleneck for AI accelerator volume, expanding through 2026 2024 Yole Advanced Packaging 2024.
The decisive variables for anyone assessing CoWoS are therefore: the rate of capacity addition versus accelerator demand; whether bridge and organic-substrate approaches let some designs step off silicon interposers; whether second sources get past ~30% of TSMC scale; and how long packaging stays the binding constraint before lithography takes over ref.
Evidence base
- Yole’s 2024 advanced packaging analysis names TSMC CoWoS capacity as the leading bottleneck for AI accelerator volume, expanding through 2026, with Samsung X-Cube and Intel Foveros each at roughly 30% of TSMC volume 2024 Yole Advanced Packaging 2024.
- Mid-2026 HBM synthesis: HBM rides on TSMC CoWoS, Nvidia booked ~55% of 2026 CoWoS, lead times 50-104 weeks, and CoWoS rather than the memory die is widely argued to be the gating constraint.
- March 2026: HBM plus CoWoS are framed as the acute 2025-26 supply constraints, CoWoS sold out through 2026, with the durable post-2028 ceiling shifting from CoWoS to ASML/EUV at fewer than ~100 EUV machines a year ref.
- ISSCC 2026: TSMC detailed an Active LSI bridge for higher-bandwidth in-package interconnect while Intel showed UCIe-S running fast die-to-die lanes over cheaper organic substrates ref.
- Yole 2024: over 60% of leading-edge AI accelerators ship as multi-die chiplet stacks by 2027, chiplet-attributed revenue $7.5B (2024) to $30B+ (2030), UCIe Phase 2 first commercial products by 2027 2024 Yole Advanced Packaging 2024.
- May 2026: Nvidia and TSMC are argued to have not raised pricing to match the value their hardware unlocks despite being the binding supply bottleneck ref.
Open questions
- Do organic-substrate die-to-die links (Intel UCIe-S) or bridge approaches (TSMC Active LSI) let a meaningful share of accelerator designs step off silicon interposers by 2028, and at what bandwidth penalty?
- Do Samsung X-Cube and Intel Foveros move materially above the ~30%-of-TSMC-volume level cited for 2024, and do they get qualified by the top accelerator buyers?
- Does TSMC begin pricing advanced packaging to the scarcity, and if so does the rent shift from Nvidia to TSMC?
- Does co-packaged optics integration (COUPE) tighten packaging capacity again after 2028 by adding photonic yield and thermal-control steps, or is it additive capacity outside the CoWoS queue?
Assessment drafted 2026-08-31 from up to 18 KB sources using the technology-scorecard framework; scores are a draft read pending review.