Compute & Logic covers the physical substrates and architectures that execute computation, from CPUs and GPUs to domain-specific ASICs, processing-in-memory, neuromorphic and analog circuits, and the 2026 evidence says the binding constraint is no longer arithmetic but memory bandwidth and data movement.
Summary
Compute & Logic sits at the root of the compute-architecture taxonomy: it is the set of design choices about how arithmetic and control are physically implemented and how operands reach them. In practice this means five families that the current literature treats as competing answers to the same question. General-purpose GPUs remain the flexible default and the workhorse of training. Domain-specific ASICs such as TPUs, Trainium, Groq and Cerebras win at scale on stable, high-volume workloads. Reconfigurable FPGAs occupy a middle ground. Processing-in-memory and near-memory architectures move computation to where the data already sits. Neuromorphic and photonic approaches remain emerging.
The organising insight of the field in 2026 is the memory wall. Applying roofline analysis to the transformer, the decisive constraint on LLM acceleration is not FLOPs: the autoregressive decode phase is bandwidth-bound, the key-value cache can rival the model weights in size, and energy is dominated by data movement rather than by the multiply-accumulate itself. That reframing explains most of the current architectural activity. Near-memory work is not a curiosity but the most promising near-term response, and the same conclusion appears outside AI: mapping normalised min-sum belief propagation decoding of a 144,12,12 bivariate bicycle qLDPC code onto a DPU-based PIM architecture yields a projected 1.071 x 10^7 decodes/s across 2,560 DPUs versus 1.22 x 10^6 decodes/s on a 16-logical-CPU baseline, an 8.8x improvement, precisely because BP over sparse Tanner graphs is a data-movement problem.
The parameters that decide outcomes here are therefore: achievable memory bandwidth and locality per watt; how much of a workload is stable enough to justify frozen silicon; the maturity of the software stack and compiler for any non-GPU target; and the speed at which a design can be specified, verified and taped out. Open-ISA and exotic-substrate efforts live or die on the third of those, not the first.
Evidence base
- 31 August 2026: roofline analysis across GPUs, TPUs, Trainium, Groq, Cerebras, FPGAs, PIM, neuromorphic and photonic platforms concludes the decisive LLM constraint is memory, not arithmetic, with PIM the most promising near-term response and no single architecture optimal across workloads.
- 31 August 2026: normalised min-sum BP decoding of the 144,12,12 bivariate bicycle qLDPC code on a DPU-based PIM architecture projects 1.071 x 10^7 decodes/s across 2,560 DPUs versus 1.22 x 10^6 decodes/s on a 16-logical-CPU baseline, an 8.8x improvement.
- 31 August 2026: RVV 1.0 silicon from SiFive, SpacemiT and T-Head beats scalar execution on BLAS, FFTW, HPL, HPCG and STREAM, but hardware-specific implementation challenges remain versus NVIDIA Grace.
- 31 August 2026: Redwood, an accelerator for single-batch low-power ultra-low-latency physical-AI inference, had its performance model, RTL, UVM environments, formal proofs, firmware and kernels autonomously generated in under two weeks, every block reaching 95% coverage.
- 31 August 2026: DeepSeq3 hierarchical circuit representation learning reduces bounded model checking solving time by 18% on large-scale benchmarks.
- 29 July 2026: the Department of Commerce announced letters of intent with seven companies for $874 million to accelerate semiconductor R&D for the compute supply chain ref; on 29 August 2026 it moved to block Chinese AI firms from remote access to advanced chips ref.
Open questions
- Does the 8.8x PIM advantage for qLDPC decoding survive the move from uPIMulator simulation and ideal syndrome measurements to real DPU hardware with measurement noise, and does it hold against a GPU rather than a 16-logical-CPU baseline?
- Is the two-week autonomous specification-to-RTL loop reproducible by a second team on a different accelerator target, and does the resulting silicon meet its performance model in fabricated form?
- Which specific hardware implementation challenges limit RVV 1.0 platforms against NVIDIA Grace, and are they microarchitectural, memory-system or compiler problems, since only the last is quickly fixable?
- Do the analog frequency-domain and rate-based neuromorphic approaches have any measured silicon results, and at what precision, given that the neuromorphic gains are stated to be bounded by arithmetic precision?
Assessment drafted 2026-08-31 from up to 11 KB sources using the technology-scorecard framework; scores are a draft read pending review.