RISC-V is an open, modular instruction set architecture that lets designers strip out, extend or specialise the CPU instruction set for a given workload, and the research literature now shows it fabricated in production nodes (Intel 16 nm, 12 nm FinFET chiplets) as the programmable substrate inside domain-specific accelerators rather than as a drop-in replacement for proprietary high-performance CPUs.
Summary
RISC-V is an instruction set architecture (ISA): the contract between compiled software and silicon. Unlike proprietary ISAs, it is published openly and structured as a small mandatory base plus optional standard extensions, and it permits vendors to add their own instructions. The sources here show all three of those properties being exercised. Standard extensions appear as named building blocks: RV32IMC for a constrained edge SoC, RV64GC for a general-purpose core, and Zfh/Zvfh for scalar and vector float16 arithmetic. The Vector Extension (RVV) provides a vector-length-agnostic programming model, so the same binary runs across implementations with different vector register widths.
Evidence base
Open questions
Assessment drafted 2026-08-31 from up to 18 KB sources using the technology-scorecard framework; scores are a draft read pending review.