Heterogeneous integration is the practice of building a system from separately fabricated dies, materials and device layers joined in a package rather than on one monolithic wafer, and it has become the main route by which AI compute, optical interconnect and even quantum hardware keep scaling once single-die scaling stops paying.
Summary
Heterogeneous integration (HI) means assembling a working system from parts made in different processes, on different substrates, sometimes in different materials, and joining them at the package or wafer-bonding level. In the electrical domain this appears as chiplets on 2.5D interposers or 3D stacks, with high-bandwidth memory placed next to logic and different chiplets built on whatever technology node suits their function. In the photonic domain it appears as III-V gain material, thin-film lithium niobate (TFLN) or InGaAs/InP photodetectors bonded or transfer-printed onto silicon or silicon nitride waveguide circuits. The motive is the same in both cases: monolithic integration forces every function onto one process that is optimal for none of them, and yield and cost penalties grow with die area.
Mechanically, the enabling steps are attachment and interconnect. Die-to-wafer bonding, micro-transfer printing and through-substrate vias (TSVs) provide the physical joins; interposers, whether silicon, organic or glass, provide the wiring. Micro-transfer printing of TFLN onto 200 mm silicon photonics wafers has been shown with 3-sigma placement accuracy of 420 nm and printing yield above 95 per cent, giving insertion loss under 2 dB across 600 phase modulators and a half-wave voltage of 4 V. A separate group has bonded TFLN into the back end of line of a fully active silicon photonics platform, co-integrating 56 GHz germanium photodetectors and 100 GHz TFLN modulators on one chip.
The parameters that decide HI are not device parameters but system ones. First, cost: partitioning a design into chiplets with mixed technologies has been shown in simulation to cut cost by up to 43 per cent, 15 per cent geometric mean, relative to homogeneous partitioning. Second, thermo-mechanics: stacked and tightly placed dies produce hot spots and warpage that placement tools must now co-optimise alongside wirelength, and TSV arrays introduce coupling, insertion loss and self-heating that full-wave simulation cannot explore at scale. Third, interface overhead: electrostatic discharge protection and inter-chiplet signalling circuitry has been the main obstacle to shrinking chiplets below 100 mm2. Fourth, trust: multi-vendor assembly fragments the supply chain and opens routes to cloning, overproduction and chiplet substitution.
The frontier is moving from electrical chiplets, which are already commercial, to photonic and quantum HI, which is not. Examples in the literature include InGaAs-on-InP balanced photodetectors integrated onto ultra-low-loss thin-core silicon nitride delay-line interferometers, ytterbium gain in aluminium oxide designed to be compatible with heterogeneous integration into standard photonic platforms, modular chiplet-based trapped-ion processors and diamond colour-centre nanophotonics bonded to photonic integrated circuits for quantum network nodes.
Evidence base
- May 2026: micro-transfer printing of TFLN across four full 200 mm silicon photonics wafers achieved 3-sigma placement accuracy of 420 nm, printing yield above 95 per cent, insertion loss under 2 dB across 600 phase modulators, and 4 V half-wave voltage.
- December 2025: first back-end-of-line heterogeneous integration of TFLN onto a fully active silicon photonics platform via trench-based die-to-wafer bonding, yielding 56 GHz germanium photodetectors and 100 GHz TFLN modulators on one chip.
- July 2025: cost-aware partitioning study finds heterogeneous integration reduces chiplet system cost by up to 43 per cent (15 per cent geometric mean) versus homogeneous technology assignment.
- November 2025: first analytical 2.5D placer jointly optimising wirelength, peak temperature and warpage reports 3 to 13 per cent lower temperature and 5 to 27 per cent less warpage than prior tools at roughly 10 times the speed, indicating that thermo-mechanics is now a first-order placement constraint.
- November 2025: ESD protection and inter-chiplet I/O circuitry identified as the main area constraint preventing chiplets shrinking below 100 mm2, with SPICE and parasitic-extraction analysis suggesting it can be simplified in future 2.5D/3D packaging.
- March 2026: co-packaged optics position paper argues packaging, thermal management and system robustness, not device performance, now dominate scalability, and that standardisation and serviceability will decide whether CPO moves beyond early deployment.
Open questions
- Do the 200 mm micro-transfer-printing yields (>95 per cent, 420 nm 3-sigma placement) hold at 300 mm and across multiple modulator generations, or do they degrade with die count and thermal budget?
- Can the ESD and inter-chiplet signalling overhead actually be simplified enough in production packaging to take chiplets below 100 mm2, or does reliability qualification block the simplification proposed in simulation?
- Does anyone converge on standards for co-packaged optics serviceability and thermal interface, given that the sources name standardisation and serviceability as decisive for adoption but report no standards activity?
- Do the thermo-mechanical co-design tools (placement, TSV surrogates, digital twins) reach sign-off-grade accuracy, or do designers keep falling back on slow full-wave and finite-element flows that limit chiplet counts?
Assessment drafted 2026-08-31 from up to 18 KB sources using the technology-scorecard framework; scores are a draft read pending review.