AI Thermal Stack Map (junction-to-ambient)

Cross-cuts: Manufacturing
last updated 2026-06-22
TIM Approach Map (every thermal-interface-material class, in-market + R&D) TIM Approach Map (e… Thermal Interface Materials (TIM) Thermal Interface M… Diamond Heat Spreader Diamond Heat Spread… Graphene Thermal Films Graphene Thermal Fi… Vapor Chambers Vapor Chambers Heat Pipes Heat Pipes Phase-Change Materials (Thermal) Phase-Change Materi… Liquid Cooling at Datacentre Scale Liquid Cooling at D… Advanced Packaging Advanced Packaging AI Therma…

Why this map exists — the comparison logic

Heat leaves an AI accelerator along a path, junction → ambient, through a stack of layers. Each layer is a distinct engineering problem with its own physics, its own competing approaches, and its own value-capture answer. The single most useful discipline:

The meta-thesis over the whole map is Thermal Stack Arms Race: the stack stays segmented — no single material or layer wins all of it. This page is the substrate that thesis reasons over; the demand-side spine is Ai Power Thermal Binding and the buy-side market is Datacentre Thermal Power Market.

The stack, layer by layer

Heat flux at the hotspot now exceeds ~1 kW/cm²; package TDP is passing 1 kW and heading to 1.8–2.3 kW (Nvidia Rubin, CES Jan 2026). Each layer below is where some of that heat is conducted, acquired, transported, or rejected.

Off-ladder — the power-converter plane (added 2 Sep 2026)

L0-L8 is one path: the accelerator’s own junction to ambient. An AI assembly has a second heat source that does not sit on it. The 48V-to-sub-1V conversion plane is mounted beneath the package, on the far side of the die from the cold plate, dissipating 3-4kW in one plane on a ~23kW part with 2mm or less of height for switches, magnetics and any thermal solution combined. It has its own junction-to-ambient path and that path terminates nowhere.

Consequence for anyone reading this map as a coverage check: a layer can be fully covered here and the assembly still be thermally bound, which is what a Cerebras architect reported in Aug 2026 (cooling the wafer is easy, cooling the converters is very difficult). Bet page: Converter Plane Thermal. Evidence: ref.

L3 — TIM2 (lid/spreader → cold plate)

L4 — Heat acquisition (cold plate / direct-to-chip)

L5 — Coolant / dielectric working fluid

L6 — Distribution (CDU, manifolds, plumbing)

L7 — Heat rejection (system → ambient) / immersion

Company placement table

The cohort, placed. L# = primary layer (secondary in parens). Status from the company page decision:. Garbled/duplicate auto-map slugs and demand-side (server OEMs, power devices) dropped — see the source note for the full raw classification.

Where the genuine early-stage venture wedge is (vehicle-agnostic, ranked by where value is held)

Frontier

See frontmatter frontier: block.

Reading list

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