Routing is the design step that decides which physical path an information carrier takes between the elements that must interact, and in quantum and wave-based substrates it has stopped being a back-end detail and become one of the main determinants of how much useful computation a chip can do.
Summary
In any layered design flow, routing is the step that turns a placed set of functional elements into a set of physical paths connecting them. Placement decides where things sit; routing decides how they talk. On a conventional die that is a wiring and congestion problem. The evidence base assembled here covers a different and harder version of the same step: routing where the carrier is a fragile quantum state, a single photon, a spin wave, or an entangled pair, and where every extra hop costs fidelity, depth or energy rather than just area.
The recurring structure is the same across platforms. Hardware offers limited connectivity (nearest-neighbour couplers, a fixed number of inter-module ports, a finite set of optical channels). Any operation between non-adjacent elements must therefore be transported. On superconducting-style hardware the default transport primitive is SWAP insertion, which inherits both depth overhead and path congestion, and compilers built on abstract SWAP models are reported to impose several times the routing overhead in circuit depth or duration. The 2026 literature attacks this from three directions at once: better compilers that route to the native gate set rather than to an idealised CX model; new routing primitives that avoid moving the computational state at all, for example using higher qudit levels as spectral buses so that a length-L nonlocal operation costs 2L+1 rather than 3L primitives; and topology engineering, where routing number and congestion are set by the spectral properties of the interconnect graph, with Ramanujan hypergraph constructions giving a routing number of Theta(log N) and affine derandomisation on Cayley graphs giving 15 to 30 per cent congestion reduction.
The parameters that decide the outcome are therefore: the connectivity degree and spectral gap of the substrate; the overhead multiplier of the transport primitive; congestion when multiple routes overlap; the physical cost per hop (fidelity loss in entanglement routing, insertion loss and crosstalk in photonics, heat in cryogenic interconnect); and whether the routing decision is made statically at compile time or dynamically online. At the physical layer these show up as hard numbers: on-chip spectral routing of retrieved telecom photons at up to 20 MHz with inter-channel crosstalk below 10^-4 in thin-film lithium niobate, and sub-kelvin substrate thermal conductivity spanning nearly two orders of magnitude between high-resistivity silicon at 5x10^-2 W/m.K and low-resistivity silicon at 8x10^-4 W/m.K at 300 mK, which bounds how densely on-chip routing can be packed in an integrated cryogenic system.
One caution on scope. The supplied sources do not cover routing as practised in conventional CMOS physical design, and they do not cover the classical EDA toolchain. They also contain a namespace collision: quantum algorithms for the capacitated vehicle routing problem concern routing as an optimisation workload, not as a step in a fabrication or design flow. Everything below is an assessment of routing as a design and interconnect step in quantum and wave-based hardware, because that is what the evidence supports.
Evidence base
- Compilers relying on abstract three-CX-unrolled SWAP models impose several times the routing overhead in circuit depth or duration, motivating routing frameworks built on canonical two-qubit representations for advanced ISAs such as sqrt(iSWAP) and ZZ(theta) (5 May 2026).
- A swap-free routing framework using higher qudit levels as orthogonal spectral buses needs 2L+1 logical routing primitives for a length-L nonlocal operation against a 3L baseline, with Boolean fan-in at depth 2L + D_g + O(1) and a state-count lower bound d greater than or equal to 2^(K+1); verified by proofs and Cirq simulation (4 May 2026).
- Routing on Ramanujan (d,r)-regular hypergraphs achieves a routing number of Theta(log N), with multi-layer 3D acousto-optic stacking using L = O(log N) overlay layers and affine derandomisation giving 15 to 30 per cent congestion reduction (5 May 2026).
- A full-stack continuous-variable optical platform with one hundred inputs demonstrated programmable routing of quantum states across 101 input modes at a 100 MHz clock, with a cloud interface and the open-source mqc3 SDK (8 May 2026).
- An erbium-doped thin-film lithium niobate microring memory achieved frequency-selective storage and routing of retrieved photons at up to 20 MHz with inter-channel crosstalk below 10^-4, 23.3 plus or minus 0.5 per cent on-chip storage efficiency for 100 ns storage, and a 277.6 plus or minus 52.6 s comb lifetime (15 May 2026).
- Measured sub-kelvin substrate thermal conductivity at 300 mK spans high-resistivity silicon at 5x10^-2 W/m.K, borosilicate and sapphire at 2x10^-3 W/m.K, and low-resistivity silicon at 8x10^-4 W/m.K, setting the thermal budget for on-chip routing in integrated cryogenic quantum systems (8 May 2026).
Open questions
- Do the higher qudit levels used as spectral buses retain coherence long enough that the 2L+1 versus 3L primitive saving survives as a fidelity saving on real hardware, or does the shorter lifetime of higher levels cancel the depth advantage?
- Does the 15 to 30 per cent congestion reduction from affine derandomisation, and the Theta(log N) routing number, hold on physically realisable acousto-optic lattices with finite move times, or only in the idealised matching model?
- Will the single-photon switching community actually adopt consistent reporting of speed, efficiency and fidelity, and when it does, which platform among quantum dots, neutral atoms, superconducting qubits and colour centres leads?
- At what routing density does the sub-kelvin thermal conductivity of the substrate, spanning 5x10^-2 down to 8x10^-4 W/m.K at 300 mK depending on material, become the binding limit on co-integrating control and readout with qubits?
Assessment drafted 2026-08-31 from up to 18 KB sources using the technology-scorecard framework; scores are a draft read pending review.