Placement is the design step that fixes where circuit elements physically sit before routing, and it is turning from a wirelength-minimisation problem into a multi-physics optimisation that decides thermal and warpage reliability in 2.5D chiplet packages and routing overhead in quantum processors.
Summary
Placement is the stage of the physical design flow in which the locations of circuit elements are chosen on a die, an interposer or a package substrate. Everything downstream depends on it: routing feasibility, total wirelength, timing closure, power, and, increasingly, thermal and mechanical behaviour. Classical placers minimise a wirelength proxy under density constraints, usually by an analytical formulation that turns the discrete assignment problem into a differentiable optimisation solved at scale.
The pressure on that formulation comes from heterogeneous integration. In 2.5D integrated circuits, multiple chiplets are packed tightly on an interposer to enable high-speed interconnects, and demand from AI and automotive applications is accelerating adoption; as chiplet counts grow, tools limited by poor scalability and reliance on slow simulations must move beyond wirelength to address thermal and mechanical reliability. ATMPlace is presented as the first analytical 2.5D placer that jointly optimises wirelength, peak temperature and operational warpage using physics-based compact models, producing Pareto-optimal placements for systems with dozens of chiplets. The parameters that decide the step are therefore: how many objectives can be folded into a differentiable cost function, how fast the physics surrogate is compared with full simulation, and how well the solver scales with element count.
Placement also exists as a physical manufacturing tolerance, not just a design abstraction. Micro-transfer printing of thin-film lithium niobate onto silicon photonics across four full 200 mm wafers achieved 3-sigma placement accuracy down to 420 nm with printing yield above 95%, insertion loss below 2 dB over 600 phase modulators, and a half-wave voltage of 4 V. Here placement accuracy is the yield-limiting parameter of a heterogeneous integration process rather than an optimisation objective.
The same word covers a third family of problems in the supplied sources: where to put qubits, links, magic-state factories, antennas or sensors. Inter-chip coupler link placement in chiplet quantum systems, hub-trap placement in neutral-atom compilers, magic-state cultivation placement in lattice surgery, and antenna placement in movable-antenna radio systems are all combinatorial-plus-continuous siting problems attacked with the same toolkit of graph methods, reinforcement learning and convex relaxations. That convergence is the reason this page treats placement as a general design primitive rather than a single EDA tool feature.
Evidence base
- ATMPlace, posted 21 November 2025, reports 146% and 52% geometric mean wirelength improvement over TAP 2.5D and TACPlace, 3 to 13% lower temperature, 5 to 27% less warpage, and approximately 10x faster runtime, for systems with dozens of chiplets.
- Micro-transfer printing of thin-film lithium niobate onto silicon photonics across four full 200 mm wafers achieved 3-sigma placement accuracy down to 420 nm, printing yield above 95%, insertion loss below 2 dB over 600 phase modulators and a 4 V half-wave voltage, reported 29 May 2026.
- InterPlace, posted 12 September 2025, reports up to 53.0% fidelity improvement and up to 33.3% reduction in combined on-chip SWAPs and inter-chip operations by optimising inter-chip coupler link placement.
- PureMagic, 4 June 2026, achieves 40% to 150% efficiency improvement over bus routing, 19% to 80% fewer logical qubits and 4.5x faster average magic state preparation by removing the static peripheral placement of distillation factories, and is up to 15x more efficient than the static scheduler DASCOT.
- A neutral-atom compiler using dynamically placed hub traps compiles, in seconds to minutes, circuits as small as nine qubits that a placement-matched SWAP-only baseline could not schedule within a practical time budget, across seventeen benchmarks, 29 May 2026.
- MAHL, posted 8 August 2025, states that agile chip design has already integrated machine learning at logic synthesis, placement and routing, while LLM-driven chiplet design remains limited by flattened designs, high validation cost and imprecise parameter optimisation.
Open questions
- Do the compact thermal and warpage models used by ATMPlace correlate with measured package temperature and warpage on fabricated 2.5D parts, and within what error band?
- How do the reported 146% and 52% wirelength gains over TAP 2.5D and TACPlace compare against a commercial production placer rather than academic baselines?
- Does the approximately 10x runtime advantage hold beyond ‘dozens of chiplets’, and where does the analytical formulation break down as element count grows?
- Can 420 nm 3-sigma micro-transfer-printing placement accuracy and greater than 95% yield be held across high-volume production lots, and what is the accuracy budget for the resulting photonic device performance?
Assessment drafted 2026-08-31 from up to 18 KB sources using the technology-scorecard framework; scores are a draft read pending review.