Photonic integrated circuits route and manipulate light in lithographically defined waveguides on a chip, and the 2026 literature shows the field has moved from proving individual devices to fighting the system-level problems (crosstalk, fabrication variability, tuning drift, missing memory, detector integration) that decide whether large circuits can be built at all.
Summary
A photonic integrated circuit (PIC) is the optical analogue of an electronic IC: waveguides etched into a thin high-index film on a wafer replace wires, and the circuit’s function comes from splitters, interferometers, ring resonators, modulators, amplifiers and detectors patterned alongside them. Where an electronic IC moves charge, a PIC moves optical fields, which buys enormous bandwidth per channel, wavelength-division parallelism and low latency, at the cost of components that are large compared with transistors and exquisitely sensitive to nanometre-scale geometry.
There is no single PIC platform. Silicon-on-insulator gives density and CMOS foundry compatibility; silicon nitride gives low loss and access to visible wavelengths; thin-film lithium niobate gives a strong Pockels effect for fast modulation; indium phosphide gives gain; and femtosecond-laser-written glass gives three-dimensional routing. Newer entrants are being pushed for specific failures of the incumbents: thin-film lithium tantalate has been demonstrated with dB/cm-scale loss and modulators flat to about 50 GHz at 532 nm, holding 5 dBm of modulated optical power for an hour where thin-film lithium niobate devices of similar structure could not, and driving 112 Gb/s over a 3 m underwater link and 64 Gb/s over 9 m. Low-confinement silicon nitride waveguides have been made by etching trenches only tens of nanometres deep in Borofloat 33 glass, filling with 50 nm of nitride and fusion-bonding two wafers to form a thick symmetric cladding, explicitly as a cost-reduction route.
The parameters that decide a PIC are propagation loss per centimetre, fibre or free-space coupling efficiency, the strength and power cost of the tuning mechanism (thermal, electro-optic, pressure, phase-change), inter-channel crosstalk, and reproducibility across a wafer. Each of these is now an active failure mode at scale. Crosstalk accumulates across cascaded components and caps integration density, which a 2026 result addresses by tailoring rib-waveguide slab thickness so that mode hybridisation cancels coupling between neighbours, demonstrated across silicon-on-insulator and silicon nitride in standard foundry processes. Fabrication deviations cause large optical response drift that compounds in cascades, and inverse-designed subwavelength geometries are the worst affected. Even thermal tuning models are wrong at the level that matters: material thermo-refractive coefficients of Si3N4 and SiO2 vary by 7% between telecom and visible wavelengths, and that material variation contributes 1.3 times more to dneff/dT than modal confinement does.
Two structural gaps recur. There is no established non-volatile memory element in photonics, so programmable circuits pay repeated optical-electrical conversion and electronic hold-power overheads. And there is no unified, fabrication-aware physical design automation stack of the kind electronics has, which is named as the limiting factor for large heterogeneous electronic-photonic chiplets.
Evidence base
- 14 May 2026: thin-film lithium tantalate waveguides with dB/cm-scale loss and modulators flat to ~50 GHz at 532 nm sustained 5 dBm modulated power for an hour, unlike comparable thin-film lithium niobate devices, and delivered 112 Gb/s over 3 m and 64 Gb/s over 9 m underwater.
- 28 May 2026: complete cancellation of coupling between adjacent standard rib waveguides via slab-thickness-engineered mode hybridisation, demonstrated experimentally across silicon-on-insulator and silicon nitride in foundry-compatible geometries.
- 5 June 2026 (posted from 6 Dec 2025 work): a femtosecond-laser-written PIC directly coupled to a room-temperature silicon SPAD array reached 41.0% system detection efficiency at 561 nm, reported as the highest among heterogeneous, hybrid and directly coupled systems, with robustness to misalignment.
- 5 June 2026: measured 7% variation in Si3N4 and SiO2 thermo-refractive coefficients between telecom and visible bands, with the material contribution to dneff/dT 1.3 times that of modal confinement, invalidating the usual non-dispersive assumption in tuning design.
- 2 June 2026: across 35 devices, conventional quasi-static DC scanning of lithium niobate photonic crystal nanobeam cavities was shown to give unreliable electro-optic tuning efficiencies due to DC drift, requiring high-frequency triangular-wave sweeps instead.
- 2 September 2022: in an SOA all-optical neuron with 7 WDM channels at 10 Gbit/s and -17.5 dBm per channel, cross-gain-modulation noise compression makes the output OSNR exceed the input OSNR when input OSNR is below about 19 dB, so amplified spontaneous emission does not accumulate without limit across layers 2022 Shi Soa Aonn Noise Depth Scaling.
Open questions
- Does the slab-engineered zero-crosstalk approach survive process-corner variation and enter a commercial PDK, or does the cancellation condition prove too tight to hold across a wafer?
- Do photonics-informed inverse lithography and automated placement measurably raise fabricated yield on large inverse-designed circuits, and by what factor against hand-designed baselines?
- Can any of the emerging non-volatile opto-electronic resistive memory candidates meet endurance, retention and insertion-loss requirements simultaneously in a PIC process?
- Does the noise-compression result that permits deep all-optical cascades hold in a physically fabricated multi-layer chip rather than an OSNR recursion emulation 2022 Shi Soa Aonn Noise Depth Scaling?
- Does room-temperature SPAD coupling scale to high mode counts, or do superconducting nanowire detectors and their cryogenics remain unavoidable for serious quantum photonics?
Assessment drafted 2026-08-31 from up to 18 KB sources using the technology-scorecard framework; scores are a draft read pending review.