SRAM is the fast, volatile, six-transistor on-chip memory that every processor’s caches and every AI accelerator’s local buffers are built from, and in 2026 it is simultaneously the performance enabler of memory-bound AI workloads and the area/energy bottleneck that a dozen emerging memory technologies are explicitly benchmarked against.
Summary
Static random-access memory stores each bit in a cross-coupled latch of transistors (classically six, hence “6T”) rather than in a capacitor like DRAM or a resistive/ferroelectric element like the emerging non-volatile memories. Because the bit is held actively by the latch, SRAM needs no refresh, reads and writes in nanoseconds or less, is built in the same logic process as the compute it sits next to, and has effectively unlimited endurance. The costs are equally structural: six transistors per bit make it the least dense memory in the hierarchy, and the latch leaks continuously, so a large SRAM array burns static power even when idle. Those two properties, fast and sparse, set the shape of every modern memory hierarchy: SRAM for registers, caches and accelerator scratchpads; DRAM/HBM for capacity and bandwidth; Flash for bulk storage.
The most useful way to read SRAM in 2026 is as the industry’s unit of account. Nearly every emerging-memory paper in this corpus states its result in SRAM-equivalent terms: SOT-MRAM bitcells with back-end-of-line read selectors achieve 10-40% area reduction and “eventually match sub-N3 SRAM”; NOR-type IGZO FeFETs reach a 10-A “SRAM-equivalent bitcell area” of roughly 0.016 um2 at 7 nm ground rules with sub-5 ns random access; two-terminal SOT-MRAM with out-of-plane torque efficiency of 0.051 at 20 nm reaches “write energies approaching SRAM at the 7nm technology node”. Parity with SRAM, not superiority, is the target being claimed, and in these papers it is reached in design-technology co-optimisation models rather than in shipped silicon.
SRAM is also increasingly a compute substrate rather than only storage. SRAM appears as one device option in heterogeneous processing-in-memory arrays alongside ReRAM, FeFET, PCM and MRAM, is assigned latency-critical attention operations in a heterogeneous SRAM-PIM plus HBM-PIM LLM accelerator, supplies the buffers feeding systolic arrays in chiplet-based DRAM-PIM modules, and has even been implemented photonically: a 1x256 bit single-wavelength photonic SRAM array in a standard GlobalFoundries silicon photonics process sustains up to 1.5 TOPS at an average 2.5 TOPS/W in system-level modelling of HPC kernels.
Evidence base
- SRAM’s core trade-off stated plainly for edge LLM inference: fast access but low density, with DRAM contending between static weights and dynamic KV cache and Flash inactive during inference, motivating hybrid ReRAM/MRAM hierarchies (2026-01-21).
- Distributed on-chip SRAM plus mesh interconnect on the Cerebras WSE-3 eliminated off-chip memory bottlenecks and produced up to 342x speedup over a single-precision port of a state-of-the-art GPU stencil solver on an A100 (2026-05-08).
- SOT-MRAM bitcells with BEOL read selectors achieve 10-40% area reduction and eventually match sub-N3 SRAM, but at a read cost of 3-5 ns extra latency (IGZO-FET selectors) or 2.5-5x energy (diode selectors) versus 2T1R (2025-08-25).
- NOR-type IGZO FeFETs deliver down to 10-A SRAM-equivalent bitcell area (~0.016 um2) at 7 nm ground rules with sub-5 ns random access, despite writability challenges and sneak-current sensing-margin penalties (2026-04-15).
- Two-terminal SOT-MRAM with out-of-plane SOT efficiency of 0.051 at 20 nm width reaches write energies approaching SRAM at 7 nm; conventional in-plane-torque SOT materials give little or no improvement over STT-MRAM (2025-12-05).
- In digital neuromorphic processors, on-chip SRAM and STT-MRAM have become significant consumers of area and energy, constituting a new memory wall that could make such processors uncompetitive at the edge (2026-04-09).
- A 4T cross-coupled FeFET differential bit-cell smaller than conventional 6T SRAM operates in volatile or non-volatile mode with 0.13 uW store power, 2 ns store time and no explicit backup-and-restore (2026-06-19).
Open questions
- Do any of the SRAM-parity claims (10-40% SOT-MRAM area reduction, 10-A SRAM-equivalent FeFET bitcells, write energy approaching SRAM at 7 nm) survive fabrication and yield at a production node, or do they remain DTCO projections?
- At what accelerator scale does on-chip SRAM stop being worth its area and energy? The neuromorphic analysis says it has already crossed that line for edge and embedded designs; is the same true for datacentre inference silicon?
- For LLM decoding specifically, how much of the KV cache genuinely needs SRAM-class latency versus HBM or PIM-attached DRAM, given HPIM’s partitioning of attention to SRAM-PIM and GEMV to HBM-PIM?
- Can nvSRAM variants such as the 4T cross-coupled FeFET bit-cell deliver leakage savings without endurance or write-disturb penalties in a real cache, and at what read margin?
Assessment drafted 2026-08-31 from up to 18 KB sources using the technology-scorecard framework; scores are a draft read pending review.