Two distinct multipliers hide inside the headline. The published grid separates them cleanly: worst case (erased cells, zero input sparsity) gives 3,452.6 TOPS/W with 95% charge recovery and 198.5 TOPS/W without; an MNIST one-layer perceptron gives 29,600 with recovery and 1,702 without. The charge-recovery assumption alone is worth about 17.4x, and the 95% figure is imported from the adiabatic-circuits literature rather than measured on this device Demasius 2021 Memcapacitor Nature Electronics. So the number you take seriously depends entirely on which assumptions you accept.
The parameters that decide CapRAM are therefore: (1) does high-efficiency charge recovery survive in real circuits at real clock rates; (2) does a multi-level analog device hold enough effective precision at manufacturable yield, given that the 2026 direction of travel in CIM is toward analog-compute with digital readout specifically to manage noise and variability, which the KB flags as a headwind for any pure analog multi-level device including this one ref; (3) whether the density story survives 3D stacking economics, where added layers stop reducing cost past a minimum Walker 2013 Rigorous 3D Nand Flash Cost Analysis; and (4) whether the incumbent baseline stands still, which it does not, with a defensible floor of ~2.5-3x per year decline in GPU delivered cost per token.
Evidence base
Open questions
Does the 95% charge-recovery assumption, which alone accounts for ~17.4x of the headline efficiency, survive measurement in a real circuit at a real clock rate, or does it collapse the way most adiabatic schemes do outside simulation?
What effective precision does a CapRAM cell hold at manufacturable yield, and can it be paired with digital readout without giving back its energy advantage, given that hybrid readout is now the industry’s route to manufacturability?
If density depends on 3D stacking, what construction and layer count does CapRAM use, and where does its die-cost minimum fall under a taper-angle-aware cost model?
Has any CapRAM test chip been taped out at 90nm or below, and does its measured energy per MAC land nearer the 198.5 TOPS/W no-recovery case or the recovery-enabled figures?
Assessment drafted 2026-08-31 from up to 12 KB sources using the technology-scorecard framework; scores are a draft read pending review.
Recent mentions
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Does the 95% charge-recovery assumption, which alone accounts for ~17.4x of the headline efficiency, survive measurement in a real circuit at a real clock rate, or does it collapse the way most adiabatic schemes do outside simulation?
What effective precision does a CapRAM cell hold at manufacturable yield, and can it be paired with digital readout without giving back its energy advantage, given that hybrid readout is now the industry's route to manufacturability?
If density depends on 3D stacking, what construction and layer count does CapRAM use, and where does its die-cost minimum fall under a taper-angle-aware cost model?
Has any CapRAM test chip been taped out at 90nm or below, and does its measured energy per MAC land nearer the 198.5 TOPS/W no-recovery case or the recovery-enabled figures?
Does CapRAM reach a product-grade test chip (named partner) or a Series A by mid-2027 — the near-dated checkpoint in the SEMRON thesis?
Is the 20× chip-level energy claim a full-chip (ADC-inclusive) number or array-only?
Does the CapRAM weight-write mechanism hold retention/endurance at the standard-CMOS interface, or drift like floating-gate flash?