3D stacking is the practice of building chips upwards rather than outwards, and it is already the dominant scaling lever in NAND flash and AI memory, but the sources show each added layer buys less density than the last and the cost per bit eventually turns back up.
Summary
3D stacking covers two related but distinct engineering families. The first is monolithic 3D: layers of devices are fabricated one above another on the same wafer, as in 3D NAND flash, back-end-of-line (BEOL) memory arrays built above the logic, and stacked-transistor schemes such as CFET. The second is package-level 3D: separately manufactured dies are thinned, aligned and bonded on top of each other, as in HBM DRAM stacks and hybrid-bonded memory chiplets. Both are responses to the same problem: planar area is expensive and lithographic shrink has slowed, so the cheapest remaining dimension is vertical.
The physics that decides monolithic 3D is deep-etch geometry. A high-aspect-ratio hole or slit cannot be etched with perfectly vertical walls, so it is wider at the top of the stack than at the bottom. Walker’s cost model shows the cell pitch at the top of the stack, which is what defines the array footprint, grows linearly in layer count through a term proportional to 2·N_L(L_g + L_s)·tanθ Walker 2013 Rigorous 3D Nand Flash Cost Analysis. More layers means fewer cells needed per layer, which shrinks footprint, but a larger top-of-stack pitch, which grows it. The two effects cross, producing a minimum in die cost beyond which adding layers makes the part more expensive, not cheaper Walker 2013 Rigorous 3D Nand Flash Cost Analysis. The same paper shows a lithography-intensive layered approach using three critical masks per device layer can reach a smaller die and undercut vertical-channel 3D NAND on total cost, which inverts the industry’s usual assumption about which route is cheap.
Production data is consistent with diminishing returns. SK Hynix’s 321-layer V9 NAND adds a third processing deck to reach roughly 44% higher density for about 30% more process steps ref. That is still a favourable trade, but it is a trade, not free scaling, and it tells you the industry has stopped trying to etch a single continuous stack.
For emerging memories the binding parameter is electrical, not geometric. A read-centric DTCO study of NOR-type IGZO FeFETs finds 3D stacking density in monolithic 3D FeNOR storage-class memory is limited by read margin, because sneak current associated with a negative program-state threshold voltage erodes sensing, requiring positive-threshold engineering such as ferroelectric layer thinning. Ferroelectric non-volatile capacitors are similarly described as having 3D stacking potential but a memory window of only 1 to 10 fF/µm and sense margins in the ±5 mV range after co-optimisation. So the ceiling on any given 3D memory is set by whichever runs out first: etch taper, process-step cost, thermal budget, bonding pitch, or the signal left at the sense amplifier.
Evidence base
- November 2013: Walker’s cost model shows 3D NAND die cost per bit does not fall monotonically with device layers; a cost minimum exists because top-of-stack cell pitch grows linearly in layer count via deep-etch taper, and a litho-intensive layered route can undercut vertical-channel 3D on total cost Walker 2013 Rigorous 3D Nand Flash Cost Analysis.
- 13 January 2026: SK Hynix’s 321-layer V9 3D NAND adds a third processing deck for roughly 44% higher density at roughly 30% more process steps; CFET is framed as the successor to gate-all-around with better-than-expected ring-oscillator and SRAM results ref.
- 15 October 2024: Yole expects eFlash to retain more than 50% of embedded non-volatile memory at 40nm and above via 3D stacking, and states FeFET does not displace HBM at the AI accelerator memory layer through 2030 2024 Yole Emerging Memories 2024.
- 5 June 2026: a read-centric DTCO study of NOR-type IGZO FeFETs reports bitcell area down to about 0.016 µm2 with 7nm ground rules and sub-5 ns random access, but finds monolithic 3D FeNOR stacking density limited by read margin due to sneak current from negative program-state threshold voltage.
- 18 June 2026: ferroelectric non-volatile capacitance memories are credited with 3D stacking potential but constrained by a 1 to 10 fF/µm memory window, with co-optimised read-out achieving about ±5 mV sense margin.
- 13 May 2026: NSF awarded $366,820 to a Purdue CAREER project using advanced three-dimensional integration and specialised memories for neuro-symbolic AI hardware.
- 31 August 2023: the chiplet market, the package-level route to 3D, was worth about $3 billion in 2021, roughly 0.5% of a $600 billion semiconductor market, twelve years after the first chiplet-architecture part in 2011 ref.
Open questions
- Where does the die-cost minimum identified by Walker actually fall for current deck-stacked architectures, and has the industry already passed it at 321 layers?
- Does positive-threshold engineering, for example ferroelectric layer thinning, raise 3D FeNOR stacking density enough to matter, or does sneak current cap monolithic 3D emerging memory at a commercially uninteresting layer count?
- Does the process-step penalty per added deck stay near the 30%-for-44% ratio, or does it deteriorate with the fourth and fifth decks?
- Do package-level stacking economics, hybrid bonding and chiplets, exhibit their own cost minimum analogous to the monolithic case, and if so what sets it: bonding pitch, yield or thermal dissipation?
Assessment drafted 2026-08-31 from up to 11 KB sources using the technology-scorecard framework; scores are a draft read pending review.