Quantum error correction encodes one logical qubit across many noisy physical qubits and uses a real-time classical decoder to infer and undo errors; it is the mandatory bridge between today’s 10^-3 to 10^-4 physical error rates and the sub-10^-9 rates practical applications need.
Summary
Quantum error correction (QEC) is the engineering answer to the fact that qubits decohere. A logical qubit is encoded redundantly across many physical qubits using a stabiliser code (surface code, toric code, or a quantum low-density parity-check code such as the bivariate bicycle family). Repeated mid-circuit measurements of the stabilisers produce a stream of parity data, the syndrome, which reveals where errors happened without measuring, and therefore destroying, the encoded information. A classical decoder then maps syndromes to the most likely correction. Below a code-dependent physical error rate called the threshold, adding more physical qubits suppresses the logical error rate exponentially; above it, more qubits make things worse.
Four parameters decide whether this works in practice. First, the gap between hardware error rates and application requirements: trapped-ion systems today sit at 10^-3 to 10^-4 while practical applications need below 10^-9, and current devices have fewer than 60 qubits. Second, decoder accuracy: belief propagation is fast but converges poorly on quantum codes because degeneracy, the existence of many equivalent corrections, confuses the message-passing. Third, decoder latency: syndromes arrive every measurement round, and if the decoder falls behind, the backlog grows without bound. Fourth, the quality of the mid-circuit measurement and feed-forward machinery itself, which QEC depends on and which is among the noisiest operations on real hardware.
The current literature is concentrated on the decoder and control layer rather than on the codes. Recent work reports belief-propagation variants improving accuracy over plain BP by two to eight orders of magnitude on topological codes, FPGA implementations decoding the 144,12,12 bivariate bicycle code at 596 ns average latency per round, and syndrome-level statistical tricks that raise thresholds and cut logical error rates by up to four orders of magnitude with no hardware change. Parallel strands cover architecture (how to lay out surface codes on modular trapped-ion machines, on neutral-atom arrays using global Rydberg pulses, and on silicon donor-cluster arrays with bias-tailored codes) and the awkward reality that hardware noise drifts in time, which QEC amplifies unless tracked.
Evidence base
- Trapped-ion systems have fewer than 60 qubits with error rates of 10^-3 to 10^-4, against a practical-application requirement below 10^-9; logical qubit demonstrations exist but are restricted to small codes and systems, and topology-aware compilation improves logical clock speed by an average 3.8X (4 May 2026).
- Lottery BP reports improving decoding accuracy over belief propagation by two to eight orders of magnitude on topological codes, with syndrome voting to compress multiple measurement rounds and mitigate decoder backlog (4 May 2026).
- An FPGA implementation of three GARI-based decoder cores for the 144,12,12 bivariate bicycle code achieved 596 ns average latency per decoding round on a VCU19P, using six times fewer resources than the previous proposal (5 May 2026).
- Syndrome resampling raised surface-code thresholds for both optimal and suboptimal decoders and cut logical error rates by up to four orders of magnitude with no hardware or decoder modification (8 May 2026).
- Encoded Clifford Trotter execution with mid-circuit stabiliser verification on a barium development system achieved up to 54% lower logical error rate, an advantage that disappeared when stabiliser readout was deferred to the end of the circuit (14 May 2026).
- Real hardware noise varies over time and QEC amplifies that drift if unaddressed; detector fire rate can be mapped to logical error rate for on-the-fly prediction without full characterisation overhead (8 May 2026).
Open questions
- Do the two to eight orders of magnitude decoder accuracy gains reported in simulation survive on hardware with realistic, drifting, correlated noise and imperfect mid-circuit measurement?
- Can a decoding layer scale from three FPGA cores for one 144,12,12 code block to a full machine within acceptable power and area budgets?
- Which code family wins on total overhead once decoder cost, architecture and compilation penalties are included: surface codes on modular hardware or bivariate bicycle and other qLDPC codes?
- Will mid-circuit measurement fidelity improve enough to stop being the dominant error source, or do measurement-free QEC schemes using multiqubit Rydberg gates become the preferred route?
Assessment drafted 2026-08-31 from up to 18 KB sources using the technology-scorecard framework; scores are a draft read pending review.