An FPGA is a chip whose digital logic is configured after manufacture, and the supplied evidence shows it is the default substrate wherever a system needs deterministic sub-microsecond processing at the edge of an instrument: quantum error decoding, particle-physics triggers, photonic feedforward, SPAD LiDAR readout and distributed MIMO basebands.
Summary
A field-programmable gate array is a fabric of small programmable logic elements (lookup tables plus registers), hard blocks such as block RAM and converters, and a configurable interconnect. The user’s circuit is described in RTL, technology-mapped to primitives, clustered (“packed”) into logic blocks, then placed and routed onto the physical fabric. Because the result is real parallel hardware rather than instructions executed on a processor, the latency of a design is fixed and known, which is the property that most of the work here is buying. The same flexibility that gives this determinism also caps it: the fabric is larger, slower and less energy-efficient than an ASIC implementing the same function, and the compile flow is slow.
The sources are almost entirely application evidence rather than device evidence, and they cluster tightly. In quantum systems FPGAs sit in the control and correction loop: a VCU19P implementation of three GARI-based decoder cores for the 144,12,12 bivariate bicycle code reaches 596 ns average latency per decoding round using six times fewer resources than the previous proposal; a fibre-based homodyne feedforward system for continuous-variable measurement-based quantum information processing achieves 196 ns total system latency; a Spartan-7 drives an open-hardware ultra-low-noise DAC module for ion-trap electrode control; external FPGA photon counting backs a 40 nm CMOS SPAD array for NV-centre biosensing. In instrumentation, PCIe-hosted FPGA cards linked by optical fibre run a 30 MHz real-time tracking prototype on live LHCb VELO data, and a CRS FPGA backplane carries 128 digitised inputs per crate over 25 Gbps lanes for the CHORD correlator. In radio, 16 AMD Zynq UltraScale RFSoC ZCU216 boards form a 256-antenna distributed MIMO testbed with real-time beamforming on the FPGA fabric.
The second cluster is compute acceleration, where the FPGA is a stepping stone rather than an endpoint. eMamba reports up to 10x speedup and 48.6x lower energy for Mamba state-space models on FPGAs and ASICs through hardware-friendly approximations, and notes no prior framework targeted Mamba at the edge 2025 08 Emamba Edge Acceleration. OpenEye is a parameterisable, sparsity-aware FPGA DNN accelerator with near-linear scaling of interconnect overhead as processing elements increase. FPGAs also serve as pre-silicon emulation vehicles: EMiX partitions a 64-core RISC-V design across eight Alveo U55c boards and boots Linux, explicitly because single-device capacity is exceeded.
The parameters that decide an FPGA deployment are latency budget, resource capacity, energy per operation and toolchain cost. Two of these are under active attack in the sources. Capacity is being addressed by die stacking into 2.5D and 3D architectures, where inter-die connection density and latency force a bespoke routing architecture that has not been well modelled until now. Toolchain cost is measurable: packing alone consumes 58% and 94% of the VPR flow runtime on average for AMD 7-series-like and Altera Stratix-10-like architectures respectively.
Evidence base
- A VCU19P FPGA hosting three GARI-based decoder cores for the 144,12,12 bivariate bicycle code achieved 596 ns average latency per decoding round with six times fewer resources than the prior proposal, the first reported multi-core correlated-error decoder on a single FPGA (5 May 2026).
- An FPGA feedforward system with a >95% quantum efficiency fibre homodyne detector reached 196 ns total system latency for continuous-variable measurement-based quantum information processing, moving adaptive operations out of post-processing (3 Jun 2026).
- PCIe-hosted FPGA cards interconnected by optical links ran a 30 MHz real-time VELO tracking prototype on live LHCb data during physics data taking, with Run 3 begun in 2022 (published 4 May 2026).
- Packing consumed 58% and 94% of total VPR flow runtime on average for AMD 7-series-like and Altera Stratix-10-like VTR architectures respectively, identifying CAD runtime as a first-order barrier (27 Apr 2026).
- EMiX partitioned a 64-core RISC-V design across eight Alveo U55c FPGAs and booted Linux, because full-system emulation of large multi-core designs exceeds single-FPGA capacity (29 Apr 2026).
- eMamba reported up to 10x speedup and 48.6x lower energy for Mamba models on FPGAs and ASICs, noting no prior hardware-acceleration framework targeted Mamba at the edge (14 Aug 2025) 2025 08 Emamba Edge Acceleration.
Open questions
- At what point does each of these workloads migrate to ASIC? eMamba reports its 10x/48.6x gains across FPGAs and ASICs jointly 2025 08 Emamba Edge Acceleration, but gives no crossover volume or NRE analysis that would let one date the transition.
- Do 2.5D and 3D die-stacked FPGAs actually relieve the capacity ceiling that forced multi-FPGA partitioning in EMiX, and at what inter-die latency penalty?
- Can packing runtime be reduced enough to change design-iteration economics, given it is 58% to 94% of the VPR flow today?
- Does on-chip programmable logic embedded with SPAD pixels displace discrete FPGAs in volume imaging, or remain a research architecture?
Assessment drafted 2026-08-31 from up to 18 KB sources using the technology-scorecard framework; scores are a draft read pending review.