Physics / mechanism
Gate-all-around (GAA) nanosheet transistors replace the FinFET’s vertical fin with a stack of horizontal silicon sheets (typically 2–5 sheets, 5–8 nm thick, 20–70 nm wide) surrounded by gate dielectric on all four sides. Full gate wrap maximises electrostatic control, suppressing short-channel effects—subthreshold swing approaches the 60 mV/dec theoretical limit at nodes below 5 nm. Drive current scales by stacking more sheets; sheet width tunes the speed/power tradeoff per design. TSMC N2 (risk production 2025), Samsung SF2, and Intel 20A/18A are first-wave GAA nodes. Gate pitch lands ~45–50 nm; contacted poly pitch ~45 nm. High-κ/metal gate and RMG integration remain the primary yield risk.
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